1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to, e.g., a static random access memory (SRAM).
2. Description of the Related Art
An SRAM is known as a type of semiconductor memory device. This SRAM uses an SRAM cell (6Tr. SRAM cell) formed by, e.g., six metal oxide semiconductor (MOS) transistors.
The 6Tr. SRAM cell comprises two inverter circuits. The output terminal of one inverter circuit connects to the input terminal of the other inverter circuit. The 6Tr. SRAM cell further comprises two transfer gates each of which connects a data storage node in the inverter circuits to a bit line in data read/write operation.
The static noise margin (SNM) is an index representing the operation margin of an SRAM. While a word line is selected and a bit line is precharged to a power supply voltage Vdd, the SNM corresponds to the length of one side of a square which can be written in a space surrounded by curves of superimposed input/output characteristics of two inverter circuits.
In the conventional 6Tr. SRAM cell, all unselected SRAM cells connected to a selected word line are disturbed while reading or writing data. This is because a storage node holding low data connects to a bit line precharged to a power supply voltage Vdd via a transfer gate. Even when the inverter circuit receives high data, the output does not drop to a low-level voltage (ground voltage Vss) due to this disturbance. This leads to a decrease in static noise margin (SNM) while reading or writing data.
Along with the advance in the micronization of a semiconductor integrated circuit, variations in a threshold voltage Vth and size (gate width and gate length) between transistors have become serious problems. The variation in characteristic between the transistors causes a variation in SNM on the low data hold side and the high data hold side. This decreases the SNM of the SRAM cell itself. The reason is as follows. That is, the SNM of the SRAM cell indicates a voltage at which data held in a storage node can withstand breakdown due to, e.g., noise. Accordingly, a smaller one of the two SNMs defines that of the SRAM cell.
From the viewpoint of element microfabrication and reduction in power consumption, the use of a lower power supply voltage for semiconductor integrated circuits is spreading. Consequently, the lower the power supply voltage, the smaller the static noise margin.
Techniques related to the above type are disclosed in reference 1 (Koichi Takeda et al., “A 16 Mb 400 MHz Loadless CMOS Four-Transistor SRAM Macro”, NEC Corp., IEEE International Solid-State Circuits Conference, 2000), and reference 2 (Kenji Noda et al., “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-μm Logic Technology”, IEEE Transactions on Electronic Devices, Vol. 48, No. 12, December 2001, pp. 2851-2855).